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Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. Paul WestergaardTimothy O. DicksonSorin P. RylovScott K. ReynoldsDaniel StoraskaBrian A. GowdaMichael Sorna: ChangIngrid Verbauwhede: A low power capacitive coupled bus interface based on pulsed signaling. James BuckwalterAli Hajimiri: Cellular handset integration - SIP vs. MRAM and microprocessor system-in-package: Observation of one-fifth-of-a-clock Cathy nguyen and jason chen hookup time of power-gated circuit.

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A study of error sources in current steering digital-to-analog converters. Ayman ShabraJeffrey C. GealowPaul F. Mike TrippT. MakAnne Meixner: Design considerations and DFT to enable testing of digital interfaces. John PekarikDavid R. GreenbergBasanth JagannathanRobert A. BreitwischDouglas D.

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CoolbaughPeter E. CottrellJohn E. FlorkeyGregory FreemanR. Opportunities and challenges in asymmetric device implementation [CMOS device scaling]. A 3D mixed-mode ESD protection circuit simulation-design methodology. BrennanJoseph N. KozhayaRobert A.

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Active-source-pump ASP technique for ESD design window expansion and ultra-thin gate oxide protection in subnm technologies. Cavalieri d'OroCarlo SamoriM. On the selection of on-chip inductors for the optimal VCO design. A word-parallel digital associative engine with wide search range based on Manhattan distance. Multiple integration method for high signal-to-noise ratio readout integrated circuit [IR focal plane array applications].

LeibowitzBernhard E. BoserKristofer S. A element CMOS imaging receiver for free-space optical communication. Aurangzeb KhanK. JayapalOanh KimM. LiHelder MakP. RileyPeter TranH. Design and development of nanometer ICs for a multi-Gigabit switching network system. KozhayaLuay Bakir: An Cathy nguyen and jason chen hookup robust method for placing power gating switches in voltage islands.

Differential transmission line interconnect for high speed and low power global wiring. A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond.

Analog IP migration using design knowledge extraction. Reviews and future prospects of low-voltage embedded RAMs. Design and implementation of an embedded KB level 2 cache subsystem.

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Amit AgarwalBipul C. PaulKaushik Roy: Process variation in nano-scale memories: Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. PopplewellMark CloutierCalvin Plett: Analysis and measurements of EM and substrate coupling effects in common RF integrated circuits. Scott HazenboomTerri S. FiezKartikeya Mayaram: Digital noise coupling mechanisms in a 2. Jan Hvolgaard MikkelsenOle K.

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