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CoolbaughPeter E. CottrellJohn E. FlorkeyGregory FreemanR. Opportunities and challenges in asymmetric device implementation [CMOS device scaling]. A 3D mixed-mode ESD protection circuit simulation-design methodology. BrennanJoseph N. KozhayaRobert A.

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Differential transmission line interconnect for high speed and low power global wiring. A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond.

Analog IP migration using design knowledge extraction. Reviews and future prospects of low-voltage embedded RAMs. Design and implementation of an embedded KB level 2 cache subsystem.

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